SmartDV™ Technologies announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a customizable tool qualification data ...

The HDL Companion version 2.0 design analysis, navigation, and, editing environment adds VHDL/Verilog linting, plus improved readability and simulation/synthesis performance. The tool automatically ...

Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, ...

In its latest incarnation, Model Technology's ModelSim 5.5 HDL simulator boasts significantly enhanced memory utilization, interactive debug features, testbench, and regression test support. According ...