EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
eTeknix

Samsung introduce new CPU, LPDDR3, CMOS sensor and NAND solutions

At the eighth annual Samsung Mobile Solutions Forum held this week Samsung introduced their range of “smart and green” products particularly their line in mobile solutions took to the forefront of the ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
Design-Reuse

Efficient logic optimization utilizing complementary behavior of CMOS gates

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...
EDN

How to Read Datasheets: Logic ICs (Part 5)

In this column, we consider the evolution of complementary metal-oxide semiconductor (CMOS) technology, which was invented by Frank Wanlass in 1963. In this column, we consider the evolution of ...